Senior Design Verification Engineer
Capgemini Polska
Poznań, Gdańsk, Katowice, Wrocław, Lublin, Warszawa, Kraków, Opole, wielkopolskie, pomorskie, śląskie, dolnośląskie, lubelskie, mazowieckie, małopolskie, opolskie
3 miesiące temu
... constrained Random and Coverage Driven Verification with UVM OVMExperience in creating ... , DDR, Serial protocols, Processor Verification etc. Expertise in one protocol ... comfortable in updating the existing verification environment for feature updates. (bring- ...
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