Senior Design Verification Engineer
Undisclosed Salary
Capgemini Polska
PL, 52.21519, 21.2453, Warszawa, mazowieckie, Warszawa
14 dni temu
... constrained Random and Coverage Driven Verification with UVM OVM Experience in ... , USB, DDR, Serial protocols, Processor Verification etc. Expertise in one protocol ... comfortable in updating the existing verification environment for feature updates. (bring- ...
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