Praca FPGA Design Engineer w Polsce. Znaleziono 25194 ofert pracy.

FPGA Developer (f/m/x)

Sii Sp. z o.o. PL, 52.21519, 21.2453, warszawa, mazowieckie, Warszawa, mazowieckie 3 dni temu

... ensure proper timing closure Optimize FPGA designs for performance, timing, and efficiency Participate in formal design reviews according to project standards ... in VHDL development and synchronous FPGA design Proficiency in synthesis and place & ...

FPGA Developer (f/m/x)

Sii Sp. z o.o. PL, 51.77497, 19.6198, łódź, łódzkie, Łódź, łódzkie 3 dni temu

... ensure proper timing closure Optimize FPGA designs for performance, timing, and efficiency Participate in formal design reviews according to project standards ... in VHDL development and synchronous FPGA design Proficiency in synthesis and place & ...

FPGA Developer (f/m/x)

Sii Sp. z o.o. PL, 50.04228, 22.00695, rzeszów, podkarpackie, Rzeszów, podkarpackie 3 dni temu

... ensure proper timing closure Optimize FPGA designs for performance, timing, and efficiency Participate in formal design reviews according to project standards ... in VHDL development and synchronous FPGA design Proficiency in synthesis and place & ...

FPGA Developer (f/m/x)

Sii Sp. z o.o. PL, 53.12348, 18.00844, bydgoszcz, kujawsko-pomorskie, Bydgoszcz, kujawsko-pomorskie 3 dni temu

... ensure proper timing closure Optimize FPGA designs for performance, timing, and efficiency Participate in formal design reviews according to project standards ... in VHDL development and synchronous FPGA design Proficiency in synthesis and place & ...

FPGA Developer (f/m/x)

Sii Sp. z o.o. PL, 54.35203, 18.64664, gdańsk, Trójmiasto, Gdańsk, pomorskie 3 dni temu

... ensure proper timing closure Optimize FPGA designs for performance, timing, and efficiency Participate in formal design reviews according to project standards ... in VHDL development and synchronous FPGA design Proficiency in synthesis and place & ...

FPGA Developer (f/m/x)

Sii Sp. z o.o. PL, 50.1024, 20.17848, kraków, małopolskie, Kraków, małopolskie 3 dni temu

... ensure proper timing closure Optimize FPGA designs for performance, timing, and efficiency Participate in formal design reviews according to project standards ... in VHDL development and synchronous FPGA design Proficiency in synthesis and place & ...

FPGA Developer (f/m/x)

Sii Sp. z o.o. PL, 52.40321, 16.93875, poznań, wielkopolskie, Poznań, wielkopolskie 3 dni temu

... ensure proper timing closure Optimize FPGA designs for performance, timing, and efficiency Participate in formal design reviews according to project standards ... in VHDL development and synchronous FPGA design Proficiency in synthesis and place & ...

FPGA Developer (f/m/x)

Sii Sp. z o.o. PL, 50.26008, 19.02547, katowice, śląskie, Katowice, śląskie 3 dni temu

... ensure proper timing closure Optimize FPGA designs for performance, timing, and efficiency Participate in formal design reviews according to project standards ... in VHDL development and synchronous FPGA design Proficiency in synthesis and place & ...

FPGA Developer (f/m/x)

Sii Sp. z o.o. PL, 53.13249, 23.16884, białystok, podlaskie, Białystok, podlaskie 3 dni temu

... ensure proper timing closure Optimize FPGA designs for performance, timing, and efficiency Participate in formal design reviews according to project standards ... in VHDL development and synchronous FPGA design Proficiency in synthesis and place & ...

FPGA Developer (f/m/x)

Sii Sp. z o.o. PL, 53.49874, 14.60616, szczecin, zachodniopomorskie, Szczecin, zachodniopomorskie 3 dni temu

... ensure proper timing closure Optimize FPGA designs for performance, timing, and efficiency Participate in formal design reviews according to project standards ... in VHDL development and synchronous FPGA design Proficiency in synthesis and place & ...

FPGA Developer (f/m/x)

Sii Sp. z o.o. PL, 51.10789, 17.03854, wrocław, dolnośląskie, Wrocław, dolnośląskie 3 dni temu

... ensure proper timing closure Optimize FPGA designs for performance, timing, and efficiency Participate in formal design reviews according to project standards ... in VHDL development and synchronous FPGA design Proficiency in synthesis and place & ...

FPGA Developer (f/m/x)

Sii Sp. z o.o. PL, 53.1928, 16.78035, piła, wielkopolskie, Piła, wielkopolskie 3 dni temu

... ensure proper timing closure Optimize FPGA designs for performance, timing, and efficiency Participate in formal design reviews according to project standards ... in VHDL development and synchronous FPGA design Proficiency in synthesis and place & ...

FPGA Developer (f/m/x)

Sii Sp. z o.o. PL, 53.02777, 18.67662, toruń, kujawsko-pomorskie, Toruń, kujawsko-pomorskie 3 dni temu

... ensure proper timing closure Optimize FPGA designs for performance, timing, and efficiency Participate in formal design reviews according to project standards ... in VHDL development and synchronous FPGA design Proficiency in synthesis and place & ...

FPGA Developer (f/m/x)

Sii Sp. z o.o. PL, 51.24645, 22.56845, lublin, lubelskie, Lublin, lubelskie 3 dni temu

... ensure proper timing closure Optimize FPGA designs for performance, timing, and efficiency Participate in formal design reviews according to project standards ... in VHDL development and synchronous FPGA design Proficiency in synthesis and place & ...

Digital design / FPGA Engineer

Antmicro Sp. z o.o. PL, 52.40321, 16.93875, poznań, wielkopolskie, Poznań, wielkopolskie 15 dni temu

Digital design FPGA Engineer Miejsce pracy: Poznań Technologies we use Expected C C++ AXI AHB APB Wishbone HDL FPGA Bash Git GCC make CMake Optional Python Operating system Linux Your responsibilities We develop modern ASIC FPGA systems composed of ...

Digital design / FPGA Engineer

Antmicro Sp. z o.o. PL, 51.10789, 17.03854, wrocław, dolnośląskie, Wrocław, dolnośląskie 15 dni temu

Digital design FPGA Engineer Miejsce pracy: Wrocław Technologies we use Expected C C++ AXI AHB APB Wishbone HDL FPGA Bash Git GCC make CMake Optional Python Operating system Linux Your responsibilities We develop modern ASIC FPGA systems composed of ...

Digital design / FPGA Engineer

Antmicro Sp. z o.o. PL, 54.35203, 18.64664, gdańsk, Trójmiasto, Gdańsk, pomorskie 15 dni temu

Digital design FPGA Engineer Miejsce pracy: Gdańsk Technologies we use Expected C C++ AXI AHB APB Wishbone HDL FPGA Bash Git GCC make CMake Optional Python Operating system Linux Your responsibilities We develop modern ASIC FPGA systems composed of ...

Experienced Product Designer

Future Mind PL, 50.26008, 19.02547, katowice, śląskie, Katowice jeden dzień temu

... learning. In our frequent internal design meetups, we share knowledge, discuss ... in app stores. Our expert engineers, designers, project managers, and analysts ... than 200 experts, lead product design projects, and develop great software ...

Experienced Product Designer

Future Mind PL, 54.35203, 18.64664, gdańsk, Trójmiasto, Gdańsk jeden dzień temu

... learning. In our frequent internal design meetups, we share knowledge, discuss ... in app stores. Our expert engineers, designers, project managers, and analysts ... than 200 experts, lead product design projects, and develop great software ...

Senior Concept Designer , Amazon Fresh Stores

Amazon Seattle, WA, US 13 godzin temu

... and customization of brand design standards as they translate into ... understand complex issues and design solutions that delight and simplify ... Creates presentation packages to communicate design and conducts design review meetings with cross-functional ...