FPGA Verification Engineer
Sii Sp. z o.o.
PL, 51.10789, 17.03854, wrocław, dolnośląskie, Wrocław, dolnośląskie
3 dni temu
... enabling project changes. Your responsibilities Develop scalable SystemVerilog UVM testbenches for ... , or SpyGlass CDC Collaborate with design, integration, DFT, and architecture teams ... UVM methodology Familiarity with SoC design elements such as ARM CSS, ...
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