Lead Analog Layout Engineer
Undisclosed Salary
Capgemini Polska
PL, 52.21519, 21.2453, Warszawa, mazowieckie, Warszawa
4 dni temu
... together a global team of engineers, scientists, and architects to help ... . in a timely manner Layout design verification including DRC, LVS, ERC, ANT and extraction Block level floor planning with design and layout engineers Top level integration and sign- ...
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